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? 2006 fairchild semiconductor corporation www.fairchildsemi.com application note AN-4150 design guidelines for flyback converters using fsq-series fairchild power switch (fps?) www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 1. introduction compared to conventional hard-switched converters with fixed switching frequencies, th e quasi-resonant converter (qrc) topology is a very attractive alternative for power supply designers. the increasing popularity of the qrc approach is based on its ability to reduce electromagnetic interference (emi) while in creasing power conversion efficiency. the fsq-series fps? (fairchild power switch) is an integrated pulse width modul ation (pwm) controller and sense fet specifically designed for quasi-resonant off-line switch mode power supplies (smps) with minimal external components. figure 1 shows the internal block diagram of the fsq-series. compared with discrete mosfet and pwm controller solution, it can reduce total cost, component count, size and weight, while simultaneously increasing efficiency, productivity, and system reliability. the fsq-series employs an advanced control technique that allows converter to operate with narrow frequency variation, while keeping the quasi-resonant operation. when the converter operates in discontinuous conduction mode (dcm), the controller finds the valley of the drain voltage and turns on the mosfet at the minimum drain voltage. m eanwhile, the converter can operate with fixed frequency when operating in continuous conduction mode (ccm), which allows converter design as simple as conventional pwm converters. this application note presents practical design consider- ations of a flyback converter employing the fsq-series fps?. it covers designing the transformer, output filter, and sync network; selecting the components; and closing the feedback loop. figure 1. block diag ram of fsq-series gnd 3 fb 8v/12v 2 8 v ref s q q r v cc v ref i delay i fb v sd v ovp sync v ocp s q q r r 3r v cc good v cc drain aocp gate driver v cc good leb 200ns pwm v burst 4 sync + - + - 0.7v/0.2v 2.5 s time delay (1.1v) lpf rc=80ns soft- start 6v 6v 0.35/0.55v + - osc 5 v str 7 6 tsd 1
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 2 2. operation principle of quasi- resonant flyback converter quasi resonant flyback converter topology can be derived from a conventional square wave, pulse-width-modulated (pwm) flyback converter without adding additional components. figure 2 shows the simplified circuit diagram of a quasi-resonant flyback converter and its typical waveforms. the basic operation principles are: during the mosfet on time (t on ), input voltage (v in ) is applied across the primary-side inductor (l m ). then, mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor as much as l m i pk 2 /2. when the mosfet is turned off, the energy stored in the inductor forces the rectifier diode (d) to turn on. during the diode on time (t d ), the output voltage (v o ) is applied across the secondary-si de inductor and the diode current (i d ) decreases linearly from the peak value (i pk n p /n s ) to zero. at the end of t d , all the energy stored in the inductor has been de livered to the output. during this period, the output voltage is reflected to the primary side as v o n p /n s . the sum of input voltage (v in ) and the reflected output voltage (v o n p /n s ) is imposed on the mosfet. when the diode current r eaches zero, the drain-to- source voltage (v ds ) begins to oscillate by the resonance between the primary-side inductor (l m ) and the mosfet output capacitor (c oss ) with an amplitude of v o n p /n s on the offset of v in , as depicted in figure 2. quasi-resonant switching is achieved by turning on the mosfet when v ds reaches its minimum value. doing this reduces the mosfet turn-on switchi ng loss caused by the capacitance loading between the drain and source of mosfet. if the transformer is designed so that the resonance amplitude is larger than v in by increasing the turns ratio, n p /n s , "zero-voltage-switching (zvs)" of the mosfet is achieved. other than turning on the mosfet with minimum drain-to- source voltage, a quasi-resonant converter provides "soft" switching conditions to the switching devices. the mosfet turns on at zero current and the diode turns off at zero current. this soft switching not only reduces the switching losses, but also lowers the switching noise caused by diode reverse recovery. the major drawback of applying a quasi-resonant converter topology is that it causes the switching frequency to increase as the load decreases and/or input voltage increases. as the load decreases and/or input voltage increases, the mosfet on time (t on ) diminishes and, ther efore, the switching frequency increases. this results in severe switching losses, as well as intermittent switching and audible noise. due to these problems, the conventional quasi-resonant converter topology has limitations for applications with wide input and load ranges. figure 2. typical waveform of quasi-resonant flyback converter 3. control method of fsq-series to overcome the frequency in crease problem at light load, fsq-series employs an advanced control technique illustrated in figure 3 with typical switching waveforms. once the mosfet is turned on, the next turn-on is prohibited during the blanking time (t b ). after the blanking time, the controller finds the valley within the detection time window (t w ) and turns on the mosfet (case b and c). if no valley is found within t w , the mosfet is forced to turn on at the end of t w (case a). thus, the converter can operate with a fixed frequency when operating in continuous conduction mode (ccm). mean while, when the converter operates in discontinuous conduction mode (dcm), the controller turns on the mosfet at the valley within t w . accordingly, the switching frequency is limited between 55khz and 67khz, as shown in figure 3 and 4. this allows converter design as simple as in conventional pwm converters. - + + v in - + v ds - l m c oss + v o - n p :n s v o n p /n s v in i ds (mosfet drain-to-source current) t d t on t s i d (diode current) i ds i d i pk d i pk n p /n s v o n p /n s v o n p /n s v in +v o n p /n s v in -v o n p /n s v ds (mosfet drain-to-source voltage)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 3 figure 3. switching waveforms of fsq-series for different input voltages figure 4. frequency variation as input voltage varies 4. step-by-step design procedure this section provides a step-by-step design process, illustrated in the design flow chart of the figure 5. figure 6 shows the basic schematic of quasi-resonant flyback converter using fsq-series, which also serves as a reference circuit for the design process described. figure 5. flow chart of design procedure t s max =18 s t b =15 s i ds i ds t w =3 s i d i ds i ds t b =15 s t w =3 s i d t b =15 s i ds t w =3 s i d i d v ds v ds v ds a b c i d i ds 55khz 67khz 59khz constant frequency a b c v in when the resonant period is 2 s ccm f s dcm 1 15 s 1 17 s 1 18 s variable frequency within limited range 1. determine the system specifications (v line min , v line max , f l , p o , e ff ) 2. determine dc link capacitor (c dc ) and calculate dc link voltage range 3. determine the reflected output voltage (v ro ) 6. determine the proper core and the minimum primary turns (n p min ) 7. determine the number of turns for each output and vcc auxiliary circuit is the winding window area (aw) enough ? y n is it possible to change the core ? y n 8. determine the wire diameter for each winding design finished 13. design the feedback control circuit 10. determine the output capacitors 5. choose proper fps considering input power and i ds peak 4. determine the transformer primary side inductance (l m ) 9. choose the secondary side rectifier diodes 12. design the synchronization network 11. design the snubber network
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 4 [step-1] define the system specifications when designing a power supply the following specifications should be determined first: line voltage range ( v line min and v line max ). line frequency ( f l ). maximum output power ( p o ). estimated efficiency ( e ff ): the power conversion efficiency must be estimated to calculate the maximum input power. if no reference data is available, set e ff = 0.7~0.75 for low-voltage output applications and e ff = 0.8~0.85 for high- voltage output applications. w ith the estimated efficiency, the maximum input power is given by: for multiple output smps, the load occupying factor for each output is defined as: where p o(n) is the maximum output power for the n-th output. for single output smps, k l(1) =1. it is assumed that v o1 is the reference output that is regulated by the feedback control in normal operation, as shown in figure 6. [step-2] determine dc link capacitor (c dc ) value and calculate the dc link voltage range in off line smps applications, a crude dc voltage ( v dc ) is obtained first on the dc link capacitor ( c dc ) by rectifying the ac mains. then, the crude dc voltage is converted into pure dc outputs. typically, th e dc link capacitor is selected as 2-3f per watt of input power for universal input range (85~265v rms ) and 1f per watt of input power for european input range (195~265v rms ). with the dc link capacitor selected, the minimum dc link voltage is obtained as: where c dc is the dc link capacitor value; d ch is the duty cycle ratio for c dc to be charged as defined in figure 7, which is typically about 0.2; p in , v line min and f l are specified in step-1. the maximum dc link voltage is given as: where v line max is specified in step-1. figure 6. basic quasi-resonant converter (qrc) using fsq-series v cc gnd drain sync pwm v fb ac in fsq-series n s2 d r2 c o2 ka431 h11a817a r d r bias r 1 r 2 r f c f l p2 c p2 v o1 v o2 d r 1 l p1 c o1 c p1 n a n p n s1 d sy r sy1 r sy2 c sy c b r cc c a d r(n) l p(n) c o(n) c p(n) n s(n) v o(n) d a d zc v str r sy3 c dc p in p o e ff ------ - = (eq 1) k ln () () (eq 2) v dc min 2 v line min () ? ? () ? ? ------------------------------------ ? = (eq 3) v dc max 2v line max = (eq 4)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 5 figure 7. dc link voltage waveform [step-3] determine the re flected output voltage (v ro ) figure 8 shows typical waveforms of the drain voltage of quasi-resonant flyback conv erter. when the mosfet is turned off, the dc link voltage ( v dc ), together with the output voltage reflected to the primary ( v ro ), is imposed on the mosfet. the maximum nominal voltage across the mosfet ( v ds nom ) is: where v dc max is as specified in equation 4. as shown in figure 8, the capacitive switc hing loss of the mosfet can be reduced by increasing v ro . however, this increases the voltage stress on th e mosfet. therefore, v ro should be determined by a trade-off between the voltage margin of the mosfet and the efficiency. it is typical to set v ro as 60~90v so that v ds norm is 430~460v (65~70% of mosfet rated voltage). figure 8. typical waveform of mosfet drain voltage for quasi-resonant converter [step-4] determine the transformer primary-side inductance (l m ) the conventional quasi-resonant converter employs a variable frequency control, which makes the optimum design of the magnetic components difficult. however, fsq- series can operate in both ccm and dcm with near constant switching frequency thanks to the advanced control technique, which allows engineers to use the conventional transformer design procedure of pwm converters. in respect of emi, dcm oper ation is preferred since the mosfet is turned on at the minimum drain voltage and the secondary-side diode is softly turned off when operating in dcm. the transformer size can be reduced when using dcm because the average energy storage is low compared to ccm. however, dcm inherently causes higher rms current, which increases the conduction loss of the mosfet and the current stress on the output capacitors. when considering efficiency as well as magnetic components size, it is typical to design the converter to operate in ccm for low input voltage condition and in dcm for high input voltage condition. the transformer primary side inductance is determined for the minimum input voltage and full-load condition. once the reflected output voltage (v ro ) is determined in step-3, the flyback converter can be simplifi ed, as shown in figure 9, by neglecting the voltage drops in mosfet and diode. the design rules are a bit di fferent for ccm and dcm. ccm design: when designing a co nverter to operate in ccm at full load and minimum input voltage condition, the maximum duty ratio is given by: where v dc min and v ro are specified in equation 3 and step-3, respectively. with d max , the prim ary- side inductance ( l m ) of the transformer is obtained as : where v dc min is specified in equation 3, p in is specified in step-1 , f s is the free-running switching frequency of the fps device, and k rf is the ripple factor, shown in figure 9. the ripple factor is clos ely related to the transformer size and the rms value of the mosfet current. it is typical to set k rf = 0.5-0.7 for the universal input range. dcm design: when designing the converter to operate in dcm at full load and minimum input voltage condition, the maximum duty ratio should be chosen as smaller than the value obtained in equation 6 , as shown in figure 9: since reducing d max increases the conduction loss in dc link voltage minimum dc link voltage t 1 t 2 d ch = t 1 / t 2 = 0.2 v ds nom v dc max v ro + = (eq 5) - v ro + + v dc - drain gnd fps + v ds - 0 v v dc max v ro v ro v ds nom l m c oss + v o - v ro v ro v ds nom d max v ro v ro v dc min + ------------------------------------- = (eq 6) l m v dc min d max ? () (eq 7) d max v ro v ro v dc min + ------------------------------------- < (eq 8)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 6 mosfet, too small d max should be avoided. once d max is determined, the prim ary-side inductance ( l m ) of the transformer is obtained as: where v dc min is specified in equation 3, p in is specified in step-1, and f s is the free-running switching frequency of the fps device. figure 9. mosfet drain current and ripple factor (k rf ) once l m is determined, the maximum peak current and rms current of the mosfet in minimum-input and full-load condition are obtained by: where p in , v dc min , d max , and l m are specified in equations 1, 3, 6, and 7, respectively, and f s is the fps free-running switching frequency. [step-5] choose the proper fps considering input power and peak drain current with the resulting maximum peak drain current of the mosfet ( i ds peak ) from equation 10, choose the proper fps f or which the pulse-by-pulse current limit level ( i lim ) is higher than i ds peak . since fps has 12% tolerance of i lim , there should be some margin in choosing the fps device. [step-6] determine the prop er core and the minimum primary turn the initial selection of the core is bound to be crude since there are too many variables. one way to select the proper core is to refer to the manuf acture's core selection guide. if there is no reference, use table 1 as a starting point. the core recommended in table 1 is t ypical for the universal input range, 55khz switching frequency, and single-output appli- cation. when the input voltage range is 195-265 v ac or the switching frequency is higher than 55khz, a smaller core can be used. for an application with multiple outputs, a larger core than recommended in the table should usually be used. with the chosen core, calculate the minimum number of turns for the transformer primary side to avoid the core satu- ration with the following : where l m is specified in equation 7, i lim is the fps pulse- by-pulse current limit level, a e is the cross-sectional area of the core in mm 2 , as shown in figure 10, and b sat is the satu- ration flux density in tesla. figure 11 shows the typical char- acteristics of ferrite core from tdk (pc40). since the saturation flux density ( b sat ) decreases as the temperature goes high, the high temperat ure characteristics should be considered. 12% tolerance of i lim should be considered. if there is no reference data, use b sat =0.3~0.35 t. since the mosfet drain cu rrent exceeds i ds peak and reaches i lim in a transition or fault condition, i lim is used in equation 14 instead of i ds peak to prevent core saturation during transition. figure 10. window area and cross-sectional area l m v dc min d max ? () 2 2p in f s --------------------------------------------- - = (eq 9) l m v dc min v ro i ds i d i m i m i m i ds i ds d max d max i d i d ro min ro dc v v+v i i rf edc i k= 2i 1 rf k = ro min ro dc v vv = + k rf < 1 i ds peak i edc i 2 ----- + = i ds rms 3i edc () 2 i 2 ----- ?? ?? 2 + d max 3 ------------- - = (eq 10) (eq 11) i edc p in v dc min d max ? ------------------------------------- - = i v dc min d max l m f s ----------------------------------- = (eq 12) (eq 13) n p min l m i lim b sat a e ----------------- - 10 6 (turns) = (eq 14) h? h?
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 7 figure 11. typical b-h characteristics of ferrite core (tdk/pc40) table 1. core quick selectio n table (for universal input range, fs=55khz and single output) [step-7] determine the number of turns for each output figure 12 shows the simplified diagram of the transformer. first, determine the turns ratio (n) between the primary side and the feedback-controlled secondary side as a reference. where n p and n s1 are the number of turns for primary side and reference output, respectively, v o1 is the output voltage and v f1 is the diode ( d r1 ) forward voltage drop of the refer- ence output. then, determine the proper integer for n s1 so that the resulting n p is larger than the n p min obtained from equation 14. the number of turns for the other output (n-th output) is determined by: the number of turns for v cc winding is determined as: where v cc * is the nominal value of the supply voltage of the fps device and v fa is the forward voltage drop of d a as defined in figure 12. it is typical to set v cc * 3~4v below v cc maximum rating (refer to the datasheet). figure 12. simplified di agram of the transformer with the determined turns of the primary side, the gap length of the core is obtained as: where a l is the al-value with no gap in nh/turns 2 ; a e is the cross-sectional area of the core in mm 2 , as shown in figure 10; l m is specified in equation 7; and n p is the number of turns for the primary-si de of the transformer. output power ei core ee core epc core eer core 0-10w ei12.5 ei16 ei19 ee8 ee10 ee13 ee16 epc10 epc13 epc17 10-20w ei22 ee19 epc19 20-30w ei25 ee22 epc25 eer25.5 30-50w ei28 ei30 ee25 epc30 eer28 50-70w ei35 ee30 eer28l 100 500 400 300 200 800 1600 0 0 magnetic field h (a/m) flux density b (mt) magnetization curves (typical) material :pc40 100 c 120 c 60 c 25 c n n p n s1 --------- v ro v o1 v f1 + ------------------------- - == (eq 15) n sn () v on () v fn () + v o1 v f1 + --------------------------------- =n s1 ? turns () (eq 16 ) n a v cc *v fa + v o1 v f1 + --------------------------- - =n s1 ? turns () (eq 17) np n s1 - v ro + d r1 n a d a n s(n) d r(n) + v o(n) - + v o1 - + v f(n) - + v f1 - - v fa + + v cc * - g 0.4 a e n p 2 10 9 l m ---------------- - 1 a l ------ ? ?? ?? ?? =mm () (eq 18)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 8 [step-8] determine the wire diameter for each winding based on the rms current of each output the rms current of the n-th s econdary winding is obtained as: where v ro and i ds rms are specified in step-3 and equation 11, respectively; v o (n) is the output voltage of the n-th out- put ; v f(n) is the diode ( d r(n) ) forward voltage drop ; d max is specified in equation 6; and k l(n) is the load-occupying fac- tor for n-th output defined in equation 2. the current density is typically 5a/mm 2 when the wire is gr e ater than 1m long. when the wire is short, with a small number of turns, a current density of 6-10 a/mm 2 is also acceptable. avoid using wire w ith a diameter larger than 1mm to avoid severe eddy curr ent losses and to make wind- ing easier. for high current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect. verify that if the windin g window area of the core, a w is enough to accommodate the wire s (refer to figure 10). the required winding window area ( a wr ) is given by: where a c is the actual conductor area and k f is the fill factor. typically the fill factor is 0.2~0.25 for single-output applica- tion and 0.15~0.2 for multiple outputs application. if the required window ( a wr ) is larger than the actual window area ( a w ), go back to step-6 and increase the core. if it is impossible to change the core due to cost or size constraints and the converter is designed for ccm and the winding win- dow ( a w ) is slightly insufficient, go back to step-4 and reduce l m by increasing the ripple factor ( k rf ). the mini- mum number of turns for the primary ( n p min ) of equation 14 decreases, which results in th e reduced required winding window area ( a wr ). [step-9] choose the rectifier diode in the secondary side based on the voltage and current ratings. the maximum reverse voltage and the rms current of the rec- tifier diode ( d r(n) ) of the n-th output are obtained as: where k l(n) , v dc max , v ro , and i ds rms are specified in equations 2, 4, step-3 and equation 11, respectively; d max is specified in equation 6; v o(n ) is the output voltage of the n- th output; and v f(n) is the diode ( d r(n) ) forward voltage. the typical voltage and current margins for the rectifier diode are : where v rrm is the maximum reverse voltage and i f is the average forward curr ent of the diode. [step-10] determine the output capacitor considering the voltage and current ripple the ripple current of th e n-th output capacitor ( c o(n) ) is obtained as: where i o(n) is the load current of the n-th output and i d(n) rms is specified in equation 22. the ripple current should be smaller than the ripple curren t specification of the capacitor. the voltage ripple on the n-th output is given by: where c o(n) is the capacitance; r c(n) is the effective series resistance (esr) of the n-th output capacitor; k l(n) , v ro , and i ds peak are specified in equation 2, step-3, and equation 10, respectively; d max is specified in equation 6; i o(n) and v o(n) are the load current and output voltage of the n-th output, respectively; and v f(n) is the diode ( d r(n) ) forward voltage. if it is impossible to meet the ripple specification with a sin- gle output capacitor due to the high esr of the electrolytic capacitor, additional lc filter stages (post filter) can be used. when using the post filters, be careful not to place the corner frequency too low. too low a corner frequency may make the system unstable or limit the control bandwidth. it is typical to set the corner frequency of the post filter at around 10- 20% of the switching frequency. [step-11] design the rcd snubber when the power mosfet is turned off, there is a high voltage spike on the drain due to the transformer leakage inductance. this excessive voltage on the mosfet may lead to an avalanche breakdow n and, eventually, failure of the fps. therefore, it is n ecessary to use an additional network to clamp the voltage. i n () sec rms i ds rms 1d max ? d max ---------------------- - v ro k ln () ? v on () v fn () + () -------------------------------------- ? = (eq 19) a wr a c k f ? = (eq 20) v dn () v on () v dc max v on () v fn () + () ? v ro --------------------------------------------------------------- - + = i dn () rms i ds rms v dc min v ro ----------- - v ro k ln () v on () v fn () + () -------------------------------------- ? = (eq 21) (eq 22) v rrm 1.3 v dn () ? > (eq 23) i f 1.5 i dn () rms ? > (eq 24) i cap n () rms i dn () rms () 2 i on () 2 ? = (eq 25) v on () i on () d max c on () f s ------------------------- i ds peak v ro r cn () k ln () v on () v fn () + () ---------------------------------------------------------- - + = (eq 26)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 9 the rcd snubber circuit and mosfet drain voltage waveform are shown in figures 13 and 14, respectively. the rcd snubber network absorbs the current in the leakage inductance by turning on the snubber diode ( d sn ) once the mosfet drain voltage exceeds the voltage of node x, as depicted in figure 13. in the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle. the capacitor used in the snubber should be ceramic or a material that offers low esr. electrolytic or tantalum capacitors are unacceptable for these reasons. figure 13. circuit diagram of the snubber network the first step in designing the snubber circuit is to determine the snubber capacitor voltage ( v sn ) at the minimum input voltage and full-load condition. once v sn is determined, the power dissipated in the snubber network at the minimum input voltage and full-load condition is obtained as: where i ds peak is specified in equation 10, f s is the fps free- running switching frequency, l lk is the leakage inductance, v sn is the snubber capacitor voltage at the minimum input voltage and full-load condition, v ro is the reflected output voltage, and r sn is the snubber resistor. v sn should be larger than v ro and it is typical to set v sn to be 2~2.5 times v ro . too small a v sn results in a severe loss in the snubber network, as shown in equation 27. the leakage inductance is measured at the switching fre quency on the primary winding with all other windings shorted. the snubber resistor with proper rated wattage should be chosen based on the power loss. the maximum ripple of the snubber capacitor voltage is obtained as: where f s is the fps free-running switching frequency. in general, 5~10% ripple of the selected capacitor voltage is reasonable. the snubber capacitor voltage ( v sn ) of equation 27 is for the minimum input voltage and full-load condition. when the converter is designed to operate in ccm under this condition, the peak drain current, together with the snubber capacitor voltage, decrease as th e input voltage increases, as shown in figure 14. the peak drain current at the maximum input voltage and full load condition ( i ds2 peak ) is obtained as where p in , and l m are specified in equa tions 1 and 7, respec- tively, and f s is the fps free-running switching frequency. the snubber capacitor voltage under maximum input voltage and full load condition is obtained as: where f s is the fps free-running switching frequency, l lk is the primary-side l eakage inductance, v ro is the reflected output voltage, and r sn is the snubber resistor. figure 14. mosfet drain voltage and snubber capacitor voltage from equation 30, the maximu m voltage stress on the internal mosfet is given by: where v dc max is specified in equation 4. np r sn c sn - v sn + v dc + - d sn drain gnd fps c dc - v ro + + v ds - l lk v x x p sn v sn () () ? -------------------------- - == (eq 27) (eq 28) i ds2 peak 2p in ? ? --------------- - = (eq 29) v sn2 v ro v ro () () (eq 30) v dc min v ro v sn v dc max v ro v sn2 i ds peak i ds2 peak minimum input voltage & full load maximum input voltage & full load i ds2 peak < i ds peak ==> v sn2 < v sn v ds max v dc max v sn2 + = (eq 31)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 10 ve r i f y t h a t v ds max is below 90% of the rated voltage of the mosfet ( bvdss ), as shown in figure 15. the voltage rating of the snubber diode should be higher than bvdss . usually, an ultra fast diode with 1a current rating is used for the snubber network. in the snubber design in this section, neither the lossy discharge of the inductor, nor stray capacitance, is considered. in the actual conv erter, the loss in the snubber network is generally less than the designed value. figure 15. mosfet drain voltage and snubber capacitor voltage [step-12] design the synchronization network the optimum mosfet turn-on point is indirectly detected by monitoring the v cc winding voltage, as shown in figures 16 and 17. the output of the sync-detect comparator (co) becomes high when the sync voltage ( v sync ) rises above 0.7v and becomes low when the v sync drops below 0.2v. the mosfet is turned on at the falling edge of the sync- detect comparator output (co). to synchronize the v sync with the mosfet drain voltage, the sync capacitor ( c sy ) should be chosen so that t q is same as a quarter of the resonance period ( t r /4 ), as shown in fig- ure 17. t r /4 and t q are given as: where l m is the primary-side inductance of the transformer, c eo is the effective mosfet ou tput capacitance, and 200ns is the internal delay time. figure. 16 synchronization circuit figure. 17 synchronization waveforms the peak value of the sync signal is determined by the voltage divider network r sy1 , r sy2 , and r sy3 as 0 v v dc max v ro v sn2 effect of stray inductance (5-10v) bvdss voltage margin > 10% of bvdss t r 4 ------ - ? ? --------------------------------- - = (eq 32) t q r sy1 r sy2 r sy3 + () ? ++ ---------------------------------------------------------- c sy ? + = (eq 33) v cc c a d a gnd drain i ds r cc r sy2 r sy3 sync v o1 c sy + v ds - n s1 n p l m + - co 0.7/0.2v d sy n a fsq-series v sync sync comparator r sy1 v ds v syns internal delay (200ns) rc time delay 0.7 v 0.2v v sync pk v ovp t q co gate meo r lc t = 42 v sync pk r sy3 r sy1 r sy2 r + sy3 + --------------------------------------------------------------- n a n s1 ----------- - v 01 v f1 + () ?? = (eq 34)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 11 where n a and n s1 are the numbers of the turns for v cc wind- ing and v o1 , respectively, and v f1 is the forward voltage drop of d 1 . choose the voltage divider r sy1 , r sy2 , and r sy3 so that the peak value of sync voltage ( v sync pk ) is lower than the ovp threshold voltage (6v) to avoid triggering ovp in normal operation. it is typical to set v sync pk to be 4~5v. [step-13] design the feedback loop since fsq-series employs cu rrent - mode control, the feedback loop can be simply implemented wi th a one-pole and one-zero compensation circuit , as shown in figure 18. in the feedback circuit analysis, it is assumed that the current transfer ratio (ctr) of the op to- coupler is 100%. the current control factor of fps, k is defined as: where i pk is the peak drain current and v fb is the feedback voltage, respectively, for a given operating condition; i lim is the current limit of the fps; and v fbsat is the feedback saturation voltage, which is typically 2.5v. to express the small signal ac transfer functions, the small signal variations of feedback voltage ( v fb ) and controlled output voltage ( v o1 ) are introduced as and . figure 18. contro l block diagram for ccm operation, the control-to-output transfer function of the flyback converter, us ing current-mode control, is given by: where v d c is the dc input voltage; r l is the effective total load resistance of the controlled output, defined as v o1 2 /p o ; n p and n s1 are specified in step-7; v ro is specified in step-3; v o1 is the reference output vol tage; p o is specified in step-1; and k is specified in equa tion 35. the pole and zeros of equation 36 are defined as: where l m is specified in equation 7, d is the duty cycle of the fps, c o1 is the reference output capacitor, and r c1 is the esr of c o1 . when the converter has more than one output, the low frequency control-to-output tran sfer function is proportional to the parallel combination of all load resistance, adjusted by the square of the turns ratio. therefore, the effective load resistance is used in equati on 36 instead of the actual load resistance of v o1 . notice that there is a righ t half plane (rhp) zero ( w rz ) in the control-to-output transfer f unction of equation 36. because the rhp zero reduces the phase by 90 , the crossover frequency should be placed below the rhp zero. figure 19 shows the variation of a ccm flyback converter control-to-output transfer function for different input voltages. this figure shows the system poles and zeros, together with the dc gain change, for different input voltages. the gain is highest at the high input voltage condition and the rhp zero is lowest at the low input voltage condition. figure 20 shows the variation of a ccm flyback converter control-to-output transfer function for different loads. this figure shows that the low frequency gain does not change for different loads and the rhp zero is lowest at the full-load condition. for dcm operation, the contro l-to-output transfer function of the flyback converter, using current-mode control, is given by: v o1 is the reference output voltage, v fb is the feedback voltage for a given condition, r l is the effective total k i pk v fb ---------- i lim v fbsat ----------------- = = (eq 35) ? f b v o1 ? v v o1 r d i d r bias r 1 r 2 i bias c b v fb 1:1 fps v o1 ' c f r f ka431 i pk mosfet current r b g vc v ? o1 v ? fb --------- = kr l v dc n p n s1 ? () ? 2v ro v dc + ----------------------------------------------------- 1s +w z ? () 1s ? w rz ? () 1s +w p ? ---------------------------------------------------------- ? = (eq 36) w z 1 r c1 c o1 ------------------- -, w rz r l 1d ? () 2 dl m n s1 n p ? () 2 ---------------------------------------- - and w p 1d + () r l c o1 ------------------ - == = (eq 37) g vc v ? o1 v ? fb --------- v o1 v fb ---------- 1sw z ? + () 1sw p ? + () ---------------------------- ? == where w z 1 r c1 c o1 ------------------- , w p 2r l c o1 ? , = = (eq 38)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 12 resistance of the controlled output, c o1 is the controlled output capacitance, and r c1 is the esr of c o1 . figure 21 shows the variation of the control-to-output transfer function of a flyback converter in dcm for different loads. contrary to the flyback converter in ccm, there is no rhp zero and the dc gain does not change as the input voltage varies. as can be seen , the overall gain, except for the dc gain, is highest at the full-load condition. the feedback compensation ne twork transfer function of figure 18 is obtained as: r b is the internal feedback bi as resistor of fps, which is typically 2.8k ; and r 1 , r d , r f , c f and c b are shown in figure 18. figure 19. ccm flyback converter control-to-output transfer function variation for different input voltages figure 20. ccm flyback converter control-to-output transfer function variation for different loads figure 21. dcm flyback converter control-to-output transferfunction variation for different loads when the input voltage and the load current vary over a wide range, it is not easy to determine the worst case for the feedback-loop design. the gain, together with zeros and poles, var ies according to the operating condition. even though the converter is designed to operate in ccm or at the boundary of dcm and ccm in the minimum input voltage and full-load condition, the converter enters into dcm, changing the system transfer functions as the load current decreases and/or input voltage increases. one simple and practical solution to this problem is designing the feedback loop for low input voltage and full- load condition with enough phase and gain margin. when the converter operates in ccm, the rhp zero is lowest in low input voltage and full-load condition. the gain increases about 6db as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. when the operating mode changes from ccm to dcm, the rhp zero disappears, making the system stable. therefore, by designing the feedback loop with more than 45 of phase margin in low input voltage and full load condition, the stability over the operating ranges can be guaranteed. the procedure to design the feedback loop is as follows: determine the crossover frequency ( f c ). for ccm mode flyback, set f c below 1/3 of right half plane (rhp) zero to minimize the effect of the rhp zero. for dcm mode, f c can be placed at a higher freq uency, since there is no rhp zero. when an additional lc filter is employed, the crossover frequency should be placed below 1/3 of the corner frequency of the lc filter, since it introduces a -180 phase drop. never place the crossover frequency beyond the corner frequency of the lc filter. if the crossover v fb ? v o1 ? --------- - w i s ----- 1sw zc ? + 11w pc ? + -------------------------- - ? = where w i r b r 1 r d c f ---------------------- - w zc 1 r f r 1 + () c f --------------------------------- ; w pc 1 r b c b --------------- ; = = ; = (eq 39)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 13 frequency is too close to the corner frequency, the controller should be designed to have a phase margin greater than 90 when ignoring the effect of the post filter. determine the dc gain of the compensator ( w i /w zc ) to cancel the control-to -output gain at f c . place a compensator zero ( f zc ) around f c /3 . place a compensator pole ( f pc ) above 3 f c . figure 22. compensator design determining the feedback circuit component includes some restrictions , such as : the voltage divider network of r 1 and r 2 should be designed to provide 2.5v to the reference pin of the ka431. the relationship between r 1 and r 2 is given as : where v o1 is the reference output voltage. the capacitor connected to feedback pin ( c b ) is related to the shutdown delay time in an overload condition by : where v sd is the shutdown feedback voltage and i delay is the shutdown delay current. th ese values are given in the product datasheet. a 10 ~ 50ms delay time is typical for most applications. because c b also determines the high- frequency pole ( w pc ) of the compensator transfer function, as shown in equation 39, too large a c b can limit the con- trol bandwidth by placing w pc at too low a frequency. a typical value for c b is 10-50nf. the resistors r bias and r d , used together with opto-cou- pler h11a817a and shunt regulator ka431, should be designed to provide proper operating current for the ka431 and to guarantee the fu ll swing of the feedback voltage for the fps device chosen. in general, the mini- mum cathode voltage and current for the ka431 are 2.5v and 1ma, respectively. therefore, r bias and r d should be designed to satisfy the following conditions: where v o1 is the reference output voltage; v op is opto- diode forward voltage drop, which is typically 1v; and i fb is the feedback current of fps, which is typically 1ma. for example, r bias < 1k and r d < 1.5k for v o1 =5v. miscellaneous notes v cc capacitor (c a ): the typical value for c a is 10-50f, which is enough for most applications. a smaller capacitor than this may result in an under-voltage lockout of fps during the startup. too large a capacitor may increase the start-up time. v cc resistor (r a ): the typical value for r a is 5-20 . in the case of multiple outputs flyback converter, the voltage of the lightly loaded output, such as v cc , varies as the load currents of other outputs change due to the imperfect coupling of the transformer. r a reduces the sensitivity of v cc to other outputs and improves the regulations of v cc . 0 db 20 db -20 db -40 db 40 db 10hz 100hz 10khz 1khz 1hz 100khz control to output f p f z f rz compensator loop gain t f zc f pc f c r 2 2.5 r 1 ? v o1 2.5 ? ----------------------- - = (eq 40) t delay v sd 2.5 ? () =c b ? i delay ? (eq 41) v o1 v op ? 2.5 ? r d ---------------------------------------- -i fb > v op r bias ------------- -1ma > (eq 42) (eq 43)
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 14 design example key design notes to maximize the efficiency, the power supply is designed to operate in ccm for minimum input-voltage and full-load condition and in dcm for high input voltage condition . 1. schematic application device input voltag e output power output voltage (rated current) dvd player fsq0365rn 85-265vac (60hz) 18.1w 5.1v (1.0a) 3.4v (1.0a) 12v (0.4a) 16v (0.3a) 3 4 c102 100nf,400v lf101 40mh c101 100nf 400v f101 fuse c103 33 f 400v r102 56k ? c104 10nf 1kv d101 1n 4007 ic101 fsq0365rn c105 47nf 50v c107 22uf 50v d102 1n 4004 r103 5 ? 1 2 3 4 5 8 9 6 12 10 11 t101 eer2828 d201 uf4003 c201 470 f 35v c202 470 f 35v l201 l203 l204 d202 uf4003 c203 470 f 35v c204 470 f 35v c206 1000 f 10v c205 1000 f 10v d203 sb360 d204 sb360 c207 1000 f 10v c208 1000 f 10v r201 510 ? r202 1k ? r203 6.2k ? r204 20k ? c209 100nf r205 6k ? ic202 fod817a bd101 bridge diode l202 vstr sync vfb vcc drain gnd 6 1 2 3 4 5 1 2 drain drain 7 8 ic201 ka431 16v, 0.3a 12v, 0.4a 5.1v, 1a 3.4v, 1a r104 12k ? tnr r105 100k ? r106 6.2k ? c302 3.3nf ac in c106 100nf smd d103 1n4148 c110 33pf 50v zd101 1n4746a r107 6.2k ? rt101 5d-9 r108 62 ? c209 47pf c210 47pf
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 15 2. transformer specifications no pin (s f) wire turns winding method n p /2 3 2 0.25 1 50 center solenoid winding insulation: polyester tape t = 0.050mm, 2 layers n 3.4v 9 8 0.33 2 4 center solenoid winding insulation: polyester tape t = 0.050mm, 2 layers n 5v 6 9 0.33 1 2 center solenoid winding insulation: polyester tape t = 0.050mm, 2 layers n a 4 5 0.25 1 16 center solenoid winding insulation: polyester tape t = 0.050mm, 2 layers n 12v 10 12 0.33 3 14 center solenoid winding insulation: polyester tape t = 0.050mm, 3 layers n 16v 11 12 0.33 3 18 center solenoid winding insulation: polyester tape t = 0.050mm, 2 layers n p /2 2 1 0.25 1 50 center solenoid winding insulation: polyester tape t = 0.050mm, 2 layers core: eer2828 (ae=86.7mm 2 ) bobbin: eer2828 electrical characteristics pin specification remarks inductance 1 - 3 1.4mh 10% 100khz, 1v leakage 1 - 3 25h max short all other pins
AN-4150 application note ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsq-series rev. 1.0.0 10/23/06 16 disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent ri ghts, nor the rights of others. life support policy fairchild?s products are not authorized for use as crit ical components in life support devices or systems without the express written approval of the president of fairchild semic onductor corporat ion. as used herein: 1.life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sus- tain life, or (c) whose failure to perform when properly used in accor- dance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2.a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. hang-seok choi, ph.d. power conversion / fairchild semiconductor phone: +82-32-680-1383 f acsimile : +82-32-680-1317 email: hangseok.choi@fairchildsemi.com

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